To program read only memory (ROM) array chips, contact, via, active region, and/or metal are implemented into (or removed from) a specific portion of selected memory cells. The “on” or “off” state of each memory cell is thus set. Each memory cell is capable of storing a binary bit of data, either in a logic state of “0” or “1” depending on whether the path of bit line to Vss of the memory cell is electrically connected or electrically isolated.
For data sensing of the ROM cells, designers use a simple scheme like a single end circuit (inverter) to detect the data state. If the ROM cell bit line has significant voltage drop (for example, to a lower voltage state from the beginning state) during a read cycle, it will represent a logical value of 1. When the ROM cell bit line keeps a higher voltage similar to the beginning state, it will represent a logical value of 0. Designer are allowed to swap the definition of “0” and “1”. However, the voltage differences between the high/low voltages are decided by drive current, leakage, stability and bit-line total capacitance of ROM cells. How to improve these factors is a challenge to future scaling.
For device improvement (drive current, leakage, and device stability), a FinFET device is the best candidate for ROM cell application. This is due to the additional sidewalls device width (for Ion performance) as well as better short channel control (for sub-threshold leakage and matching performance).
However, device performance and reliability are issues when moving to new technology nodes with higher packing density. Therefore, there is a need for a new structure and method for ROM cells to address these concerns for high-end cell application and improved multiple fins cell size.